11th June 2021 AI outperforms humans in microchip designs Researchers from Google report a new machine learning technique for microchip floorplanning that can outperform human experts.
Floorplanning is the process by which an integrated circuit is designed using a top-down view. Rather like the architectural plan of a home, garden, and walkways, each of the major functional blocks is placed in a schematic representation that provides a guide for where everything needs to be. This layout can include transistors, capacitors, resistors, wires and other components, all packed into extremely tiny spaces. Determining the optimal configuration for processing speed and power efficiency is a detailed and lengthy task, involving many iterations. It can often take weeks or even months for expert human engineers. Attempts to fully automate the process have been unsuccessful. However, researchers from Google have this week reported a new machine-learning approach to floorplanning. Not only does it reduce the design workload to a matter of hours, it also results in chips with superior designs.
Today's microchips contain a combination of standard cells, alongside what are known as macro blocks. The standard cells contain tens of millions of logic gates, while the macro blocks hold memory and tend to number in the thousands. The difference in size between standard cells and the much larger macro blocks makes their placement extremely challenging. Adding to this intricacy is wiring routes of incredible complexity. For this new study, the researchers estimated that the number of possible configurations of macro blocks is 10 to the power of 2,500. By comparison, the total number of "state spaces" possible in the board game Go is 10 to the power of 360. Furthermore, the number of components needed on a chip is growing at a rate of about 1% per week, thanks to Moore's Law. There is therefore an urgent need to automate the process of floorplanning. The Google team developed a deep neural network, trained with reinforcement learning to place macro blocks, one by one. This AI worked by assessing the current "state" of its chip layout, using this partial floorplan combined with information learned in prior steps, to determine the optimal action to take next. The AI, pre-trained on a set of 10,000 chip floorplans, placed the macro blocks sequentially in decreasing order of size. By the end of the study, it had learned to complete a chip floorplan in just six hours, while also achieving a 3% reduction in the length of wiring compared to a human engineer. The design it produced is strikingly different to conventional layouts, as seen in the diagram above (Ariane RISC-V processor), with smaller blocks in a more scattered configuration surrounding a central void. "Our method was used to design the next generation of Google's artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation," the researchers write. "We believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields." Their study is published in the journal Nature.
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